When is 3D 2B?

A KEY FACET of ‘‘More than Moore’’ scaling comes under the heading of ‘‘3D’’ the stacking of multiple integrated-circuit dies using through-silicon vias (TSVs). Stacked-die products reached the marketplace decades ago, but with peripheral I/O on individual dies and interchip interconnect on the ‘‘side’’ of the stack. TSVs are a game changer, with diameters and pitches that permit thousands of through-silicon interconnects per square millimeter of die area. The ITRS (International Technology Roadmap for Semiconductors; http://www.itrs.net) now roadmaps TSV technology in its ‘‘Interconnect’’ and ‘‘Assembly and Packaging’’ chapters. Today, TSV-based CMOS image sensors are already in mass production. The DRAM roadmap has taken on a ‘‘vertical’’ hue as well, since further horizontal scaling conflicts with cell capacitance and aspect ratio requirements. It is likely that by next year, we will see TSV-based DRAM, flash, wireless, and TV products. The promises of 3D integration are compelling. First, new and exciting form factors imagine a teraflop in a cubic centimeter! Second, heterogeneous multitechnology integration imagine logic, memory, and RF integrated without any sacrifice of circuit quality due to the constraints of having only one manufacturing process! Third, unprecedented I/O performance imagine how processor architectures can change when off-chip memory access requires 2 nanoseconds instead of 30! With nascent wide I/O interfaces and very conservative 10-micron-diameter TSV technology, off-chip interfaces can achieve equivalent capacitance as low as tens to hundreds of femtofarads, without ESD protection. Fourth, improved scaling of interconnect imagine that systems can escape the ‘‘Flatland’’ of 2D integration, so that global wires need not grow unnecessarily long! (A 3D-embedded system can have a Rent parameter of up to p 1⁄4 0.67 without ‘‘dilation’’ of wire lengths; in 2D this limit is only p 1⁄4 0.5.) These considerations potentially make 3D a low-power, low-cost, enabling technology for applications that range from immortal sensor nodes to exascale supercomputing, from green energy harvesting to implanted medical diagnostics. Whenever I get a bit pessimistic about looming capex, variability, and throughput costs of, say, triplepatterned 15-nm logic ICs not to mention the nonscaling of analog circuits and supply voltages and synchronization paradigms I tell myself that mainstream TSV-based 3D has to be (‘‘2B’’) just around the corner. One day, integration levels will reach a level such that it will be difficult to find suppliers who have all the IP blocks needed by a given system enabled for a single-die solution. One day, cost-reliability-performance trade-offs will make 3D an obvious first choice for some applications. One day, system implementers will think 3D first, and then see whether 2D is really needed for the solution. But before ‘‘one day’’ dawns, a number of obstacles must be overcome. Test and yield issues include the ‘‘known good die’’ problem: that is, how to ensure that each piece of silicon in the system can be tested, both functionally and parametrically, in isolation. Wafer-to-wafer integration strategies face the challenge of compounded yield losses from each tier of the 3D stack. Thermal and thermomechanical issues stem from the absence of good thermal pathways by which heat can be removed. Peak temperatures and temperature gradients significantly worsen with 3D stackeddie integration. This raises the specter of increased reliability risks, ranging from cracked vertical connections due to differences in thermal expansion The Road Ahead